Low Cost Wafer Bumping of GaAs Wafers
نویسندگان
چکیده
The microelectronics industry has implemented a significant number of process technologies to accomplish the various packaging and backend operations. These technologies have been successfully implemented at a number of contract manufacturing companies and also licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon based semiconductors which are based on either aluminum or copper interconnect metallurgy. The direct transfer of these technologies to compound semiconductor devices, like GaAs, LiTaO3, and GaN, is limited due to a number of technical compatibility issues and several perceived compatibility issues [1-4]. From a technical standpoint, many of these high end devices contain fragile air bridges, gold bond pads, cavities & trenches, and unique bulk material properties which are sensitive to many of the mechanical and chemical processes associated with many of the standard packaging operations using for silicon wafers. Special care must be taken to ensure that there is no mechanical stress put on the wafer during any of the handling operations associated with deposition of the UBM, solder bumping, wafer thinning, dicing, and die sort. In addition, many chemicals used for resist stripping, metal etching, and solder fluxing will react with some of the materials on these compound semiconductor devices. From a perception standpoint, companies which are processing large numbers of silicon based semiconductor wafers in their packaging and backend facilities, are reluctant to process many of these compound semiconductors because there is a perceived issue with cross contamination between the different wafer materials. Companies are not willing to risk their current business of processing silicon wafers by introducing these new materials into their existing process flow. The strategy in this study is to protect all structures and surfaces with a resist or film as part of each step in the process. This protects the wafer from mechanical and chemical damage; and at the same time protects sensitive fab processes from contamination by the compound semiconductor. Introduction The test vehicle for this program is a GaAs device which contains both air-bridges and has gold bond pads. If solder were deposited directly onto the gold bond pads, the gold would be partially consumed during the solder reflow process, and will eventually fail in the field due to thermal and electro-migration processes. An under-bumpmetallization (UBM) is required to keep these destructive processes form occurring. Schematic drawing of GaAs test vehicle and an optical image of a gold bond pad on the device. Air Bridge Bond Pad Dicing Street
منابع مشابه
A Bumping Process for 12" Wafers
A driving force to achieve increased speed and performance along with higher I/O count is the Flip Chip (FC) Technology which has therefore an high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is essential to use low cost bumping techniques. This paper shows a low cost wafer level bumping process ...
متن کاملA Roadmap to Low Cost Flip Chip Technology and Chip Size Packaging using Electroless Nickel Gold Bumping
Flip Chip (FC) Technology is gaining an increased level of importance for a variety of applications based on Flip Chip on Board or Flip Chip in Package. The first driving force for the introduction of this Technology was the need to achieve increased speed and performance along with higher I/O count. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is...
متن کاملAn Overview of Pb-free, Flip-Chip Wafer Bumping Technologies
To meet the European Union Restriction of Hazardous Substances (RoHS) requirements and the continuing demand for lower costs, finer pitch and high reliability flip chip packaging structures, considerable work is going on in electronic industry to develop Pb-free solutions for flip chip technology. In this paper, various solder bumping technologies developed for flip-chip applications are review...
متن کاملGrowth of silver nanowires on GaAs wafers.
Silver (Ag) nanowires with chemically clean surfaces have been directly grown on semi-insulating gallium arsenide (GaAs) wafers through a simple solution/solid interfacial reaction (SSIR) between the GaAs wafers themselves and aqueous solutions of silver nitrate (AgNO(3)) at room temperature. The success in synthesis of Ag nanowires mainly benefits from the low concentration of surface electron...
متن کاملSolid-state reaction-mediated low-temperature bonding of GaAs and BnP wafers to Si substrates
We report a low-temperature wafer bonding method for the realization of integration of GaAsand InP-based optoelectronic devices with Si microelectronic devices. This method uses a Au-Ge eutectic alloy as the bonding material sandwiched between GaAs and Si wafers, and between InP and Si wafers. The bonding process was carried out at 280-300 “C by taking advantage of the low-temperature solid-sta...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2010